IBIS Macromodel Task Group Meeting date: 13 August 2024 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark * Wei-hsing Huang Aurora System: * Dian Yang Raj Raghuram Cadence Design Systems: Ambrish Varma Jared James Dassault Systemes: Longfei Bai Google: Hanfeng Wang GaWon Kim Intel: Michael Mirmak * Kinger Cai Chi-te Chen Liwei Zhao Alaeddin Aydiner Sai Zhou Keysight Technologies: * Fangyi Rao Majid Ahadi Dolatsara Stephen Slater Ming Yan Rui Yang Marvell: Steve Parker Mathworks (SiSoft): * Walter Katz Graham Kus Micron Technology: Justin Butterfield Missouri S&T: Chulsoon Hwang * Yifan Ding Zhiping Yang Rivos: Yansheng Wang SAE ITC: Michael McNair Samsung * Jun-Bae Kim Siemens EDA (Mentor): * Arpad Muranyi * Randy Wolff Signal Edge Solutions Benjamin Dannan Teraspeed Labs: [Bob Ross] Zuken USA: * Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - Jun-Bae Kim introduced himself. He is a circuit design engineer interested in improving PI, and he is interested in the recent addition of SPIM (BIRD223.1). ------------- Review of ARs: - None. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the August 6th meeting. Arpad moved to approve the minutes. Dian seconded the motion. There were no objections. -------------- New Discussion: BIRD220.1 update: Yifan briefly reviewed the changes in bird220.1_v3_0812.docx, which she had sent to the ATM list. She noted that, per a suggestion from Fangyi, the derivation in Other Notes now describes the pre-driver PSIJ (delta t) as a function of the time-averaged power rail noise (delta Vcc). This derivation better reflects the changes introduced in the previous draft, in which jitter sensitivity (s/V) tables were replaced with tables of jitter values (s) vs. Vcc voltage deviation. Fangyi said the changes looked good. Adding Support for Power Delivery Modeling: Kinger recalled that BIRD223.1, accepted in November of 2023, introduced SPIM (streamlined power integrity modeling). He said BIRD223.1 contained support for AC and DC analysis. He noted that he had recently discussed the idea of adding support for transient analysis. The topic was discussed in ATM, and he had presented "Add Support of Transient Analysis to SPIM" at the IBIS Summit held in conjunction with IEEE EMC+SIPI on August 9, 2024, in Phoenix, AZ. Kinger said he wanted to discuss a new topic, adding support for Power Delivery analysis to SPIM. He noted that he had presented "Add Support of Power Delivery (PD) Analysis in IBIS" at same summit. (see https://urldefense.proofpoint.com/v2/url?u=https-3A__ibis.org_summits_aug24_&d=DwIGAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=DcQR-qLpQg5lIreuM6-NYECRIAFXt268PRNS5WO043M&m=SeHFo84whnWL9tjzF0KrTZUJbqAcWYT7fBJiLL3ttXY2foHekrxzAz0LhbTeCcTv&s=3zjPXULP8ej6uKRomFwbBCns9fet0GtJuIL5pGcnMFU&e= for both presentations) Kinger said support for standardizing Power Delivery Analysis came from many stakeholder companies in the industry, as demonstrated by the list of co-authors of the presentation. He noted that Zhiping had proposed the idea of standardizing the modeling of all components that exist in a PDN. Kinger reviewed the presentation. He noted that power consumption and loss is of critical importance to things such as battery life and thermal management, data center power consumption, electric vehicle performance, etc. He said that on a typical graphics card approximately 2/3 of the area might be used for power delivery components and only 1/3 used for the actual Silicon for the processor. He reviewed a figure compiled by Zhiping showing the trend in processor power consumption and an example of a single socket delivering 2700W. slide 6: Power Components in system PD Kinger reviewed lists of common passive and active components and some of their uses in PD design. He said they would also like to consider modeling PMIC controllers, batteries, wired and wireless charging, DC-DC converters and other components. He referred to some past presentations on modeling some of these components (slide 7). Kinger said this was a call to action for experts in PI, PD, batteries, etc. He said we need to come to agreement on what component models are needed in the PDN path. Then individual experts could assume ownership of the development of a standardized model for one (or more) of the components. Arpad said the request made sense, but he said the lengthy list of components seemed like we'd just be back to a full SPICE simulator. He said SPICE models for all of these components exist. He said in IBIS we tend to focus on behavioral models. He asked whether, for a DC-DC converter for example, Kinger was envisioning a detailed circuit description or a black box behavioral model. Kinger said for simple passive devices (e.g., R, L, C, etc.) things are well defined, but if current models are insufficient for a particular passive component then we may need to improve the models. For active components, the industry has complicated models that may be analog SPICE and behavioral hybrids. He said he wanted a lightweight behavioral model, not a detailed analog model, for intellectual property protection. He said a black box DC-DC converter model might be as simple as two equivalent sets of IR values. However, a simple model that may be sufficient for PI design might not be sufficient for power consumption modeling. Walter said the overall PI problem has many facets. He said components like VRMs can be very complex, and PDNs are very complex, and he didn't think they fit very well in the world of I/O buffers. We need some place to describe, behaviorally or otherwise, all of these power components, and an .ibs file might not be the place to do it. We might decide that we need various models related to power distribution, and we may want a whole new specification for this. He noted that IBIS [Component]s contain loads, and we may choose to put some DC load information, etc., in the IBIS file, but he suggested we consider creating a new standard for power delivery information. Kinger said he agreed that if we put power delivery modeling information in the .ibs file, we might interfere with the original purpose of IBIS. Kinger suggested that we might do something similar to the way we handled SPIM. The .ibs file might refer to information in a SPIM file, but SPIM information itself (SPIM keywords, etc.) is only allowed in a separate .spim file. He suggested that models for power delivery specific devices could be placed in the SPIM file. Fangyi said we could come up with behavioral descriptions for some active components. He asked whether Kinger would also want to include connectivity information or particular circuit topologies. He said that if we define the topology of the PDN network, then we lose flexibility. If we don't define the topology and only define individual components, then the component definitions can go in another file, as Walter suggested, and the user can connect them manually. Kinger agreed that PD exclusive components could be placed in .spim files. Arpad noted his recurring question from the original SPIM discussions. He said VRMs are typically in kHz or perhaps low MHz for switching supplies. He said our normal IBIS SI simulations are often in the GHz range. How are the two time scales for SI and PI simulated simultaneously? Walter said the sample answer is that they are not. He said the simulation flow is a two-step process. First, the PI is simulated, and you end up with voltage supply variations. Then, you take the supply rail voltage variation waveforms back as inputs to the final SI simulation. You might use the PSIJ sensitivity transfer function (BIRD226) to compute a jitter distribution from the supply waveform variations, for example. Kinger shared a "status quo client PI|PD" slide, which showed a power supply rail variation in response to a step function increase in the current drawn. Kinger said the current step might correspond to switching from low power mode to active mode, or a DDR interface switching to a higher data rate. The slide showed two different supply rail variation waveforms corresponding to different VRMs. Kinger said for real world PI design you try to cover the worst case. Walter said the problem is that you may use more expensive VRMs than necessary if you design everything for the max case. Arpad asked how you would incorporate this time varying supply rail variation if you want to use an AMI simulation. Kinger said you would use statistical techniques to fold it back into an AMI simulation. You could use PSIJ sensitivity to convert the supply waveform variation to a jitter distribution. Kinger noted that this slide illustrated a simplified scenario and the effects from just one circuit block. In a full simulation there are many circuit blocks hooked up together, and we are interested in the total power supply noise induced on each particular rail. Fangyi noted that sinusoidal jitter, for example, is time varying, but we can incorporate that into an AMI simulation. - Walter: Motion to adjourn. - Curtis: Second. - Arpad: Thank you all for joining. New ARs: Kinger: Send his "Add Support of Power Delivery (PD) Analysis in IBIS" to the ATM list. ------------- Next meeting: 20 August 2024 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives